1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor or other integrated circuit device, and.more particularly, to a method of logic simulation in design processes conducted prior to fabrication onto a semiconductor wafer, and a method of calculating delay time for a logic circuit.
2. Description of the Related Art
Semiconductor integrated circuit devices are steadily reaching higher levels of integration. Alongside this, ASICs (Application Specification Integrated Circuits), such as gate arrays, embedded arrays, standard cells, and the like, are also becoming increasingly complex.
In a standard ASIC design, logic data for a plurality of cells or macro cells designed according to certain design rules, and corresponding physical data such as pattern data etc., are set in a library, and logic design is carried out using cells and macro cells previously recorded in this library. Therefore, in the delay time calculating process and logic simulation process conducted after logic design, the calculating tools and logic simulation tools provided according to the design rules are used.
A semiconductor integrated circuit is designed by a design automation process using the data library and program tools described above, and the operation of the circuit is then verified. Thereupon, an actual pattern for forming an actual chip is designed according to this design data, and the manufacturing process then moves onto the process of actual fabrication onto a semiconductor wafer.
However, in recent years, techniques have been proposed for manufacturing ASICS, wherein large-scale macros designed according to third party design rules are buried in a chip. Namely, in these techniques, rather than just cells or macro cells (large-scale cells) from a given library, a large-scale macro, e.g. an ALU, CPU or MPU, designed on the basis of completely different design rules, is buried in the same chip. These large-scale macros may be recorded in a library along with standard cells from the ASIC vendor, or third party macros obtained from the client may be used in combination with standard cells from a library.
Macros which have a certain value in the market and are standardized may be used more frequently, but there is also a demand for the use of macros, which are not valued in the market, but which are either existing macros or third-party designed macros, etc., in order to reduce the design steps involved for the client.
In this case, the question of how to carry out a logic simulation for verifying the operation of the chip as a whole presents a significant problem. In particular, in the process of calculating the delay time in the circuit network, which is necessary for carrying out a logic simulation, it is a very difficult problem to determine how to merge (combine) macros based on different design rules with standard cells.
A simple method would be start by implementing a characterizing process for determining respective delay parameters for all internal cells in the third party macros, and then to calculate the delay time for the chip as a whole using these characterized delay parameters. However, a method which involves a characterizing process from the start for all cells in large-scale macros would require an extraordinarily high number of steps, and is not compatible with the objective of using existing third-party macros. Therefore, a method which resolves these problems is sought.
A process for calculating delay time conducted after logic design and prior to the aforementioned logic simulation process would lead to variations in circuit threshold voltage in the cells and macros in the chip as the chip grows in scale, thereby increasing complexity.
In other words, the delay time for cells or macros (circuit units comprising a plurality of cells) varies depending on the input through-rate of the input signal supplied to the input terminal and the load capacitance connected to the output terminal. Furthermore, the output through-rate generated at the output terminal varies depending on the aforementioned input through-rate and the load capacitance connected to the output terminal. Therefore, in order to discover the delay time in the cells and macros, it is necessary to form a logic circuit and then determine the input through-rate found from the output and connections from the previous circuit stage, and the load capacitance of the next circuit stage connected to the output terminal. The input-side parameter for determining the delay time of the cell according to this input through-rate and the load capacitance, and the output-side parameter for determining the output through-rate for the cell similarly according to the input through-rate and the load capacitance are recorded in the cell library.
However, if the circuit threshold voltage varies for each cell or macro, as described above, then it becomes necessary to incorporate in the aforementioned delay time calculating process a step of determining the delay time according to a different threshold voltage for each cell, and a step of making corrections for mismatching between the threshold voltage of the previous circuit stage and the threshold voltage of the next circuit stage. If, in order to avoid this, the delay time is determined by setting an average threshold voltage for all the cells, there will be mismatching between the threshold voltages of the actual cells and the aforementioned average threshold voltage, and in cases where the cell delay times are extremely short, negative values may be produced.
Such negative delay times are not suitable and converting them unconditionally to zero means that the delay times in the logic circuit will ultimately be inaccurate.